Compared with the traditional mixed mode test, the test power caused by pseudo-random test patterns was decreased. 与传统的混合测试模式相比，克服了伪随机测试阶段带来的功耗问题。
In this paper, based on the build-in self-test for logic circuits, a new approach is proposed to reduce pseudorandom test sequence length. 本文建立在逻辑电路内部自测试的基础上，提出了一种新的缩短伪随机测试序列长度的方法。
